| 摘要 |
The memory device includes two driver transistors (Q3,Q4), two access transistors (Q1,Q2), two load transistors (Q5,Q6), and two conductive layers. One conductive layer (3a,3b) includes a polysilicon layer and is provided to the gate electrodes of the driver transistors and the load transistors. The other conductive layer, e.g. a word line (9a), also serves as a gate electrode to the access transistor and is also provided with a polysilicon layer. Also provided with this latter layer is a current source wiring (9d) and connection wiring 9b,9c to connect the n-type MOS active region (1). The driver and access transistors are provided within the n-type active region while the load transistors are provided within a p-type region (6).
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