| 摘要 |
The present invention provides a communication controller of a higher rate, which enables a data transfer at the maximum bus width if an inconsistency of data alignment is present, when DMA transferring a communication frame with its header and payload data into respective exclusive memory space. To achieve this, an aligner ALIGN is provided on the bus between the DMA controller and the main memory MAINMEM. The aligner ALIGN is comprised of a selector RXSEL for selecting 32 bits of data from the register RX_REG for storing data of previous writing and from the DMAC data bus to output data to the bus of main memory MAINMEM, a selector TXSEL for selecting 32 bits of data from the register TXREG for storing data of previous reading and from the CPU data bus to output data to the DMA bus, an inconsistent alignment detector circuit ALGN_CHK for detecting the inconsistency of alignment to determine the signal lines to be selected by the selector, and an address generator ADR_CNV for generating address signals for the CPU from the address signals of the DMAC. Since transfer at the maximum bus width is enabled even when the inconsistency of alignment is present, transfer may be performed in the time and number half of the conventional controller.
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