发明名称 Method for manufacturing semiconductor integrated circuit device
摘要 Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.
申请公布号 US2003045088(A1) 申请公布日期 2003.03.06
申请号 US20020195716 申请日期 2002.07.16
申请人 HITACHI, LTD. 发明人 IMAI TOSHINORI;FUJIWARA TSUYOSHI;SHIRAISHI TOMOHIRO;ASHIHARA HIROSHI;YOSHIDA MASAAKI
分类号 H01L23/52;H01L21/3205;H01L21/60;H01L21/768;H01L23/485;(IPC1-7):H01L21/476;H01L21/44 主分类号 H01L23/52
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