发明名称 |
A MULTIPROCESSOR INFRASTRUCTURE FOR PROVIDING FLEXIBLE BANDWIDTH ALLOCATION VIA MULTIPLE INSTANTIATIONS OF SEPARATE DATA BUSES, CONTROL BUSES AND SUPPORT MECHANISMS |
摘要 |
A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.
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申请公布号 |
WO03019399(A1) |
申请公布日期 |
2003.03.06 |
申请号 |
WO2002US27430 |
申请日期 |
2002.08.27 |
申请人 |
INTEL CORPORATION |
发明人 |
ROSENBLUTH, MARK;WOLRICH, GILBERT;BERNSTEIN, DEBRA;WILDE, MYLES;ADILETTA, MATTHEW |
分类号 |
G06F13/00;G06F13/364;G06F13/40;G06F13/42;(IPC1-7):G06F13/40 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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