发明名称 |
Nonvolatile semiconductor memory device that can suppress effect of threshold voltage variation of memory cell transistor |
摘要 |
In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.
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申请公布号 |
US2003043629(A1) |
申请公布日期 |
2003.03.06 |
申请号 |
US20020200773 |
申请日期 |
2002.07.24 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TOMOEDA MITSUHIRO;OHBA ATSUSHI;MAKINO TOSHIMASA |
分类号 |
G11C16/02;G11C16/06;G11C16/14;G11C16/16;G11C16/34;(IPC1-7):G11C11/34 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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