发明名称 Digital event sampling circuit and method
摘要 A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second time interval within the first time interval. A delay timer, coupled between the first and second timers, pseudo-randomly delays initiation of the second timer from the start of the first time interval. In one embodiment, the first timer is an (N+1)-bit binary counter. The delay timer includes an N-bit round robin latch and seeded by a pseudo-random number generator having fewer than N bits, the round robin latch shifting its contents to form an N-bit pseudo-random number. The second timer is initiated when the value of the first timer is equivalent to the round robin latch. A coincidence circuit passes digital event pulses during the second time interval. A count is accumulated of the sampled digital event pulses.
申请公布号 US2003046627(A1) 申请公布日期 2003.03.06
申请号 US20010934891 申请日期 2001.08.22
申请人 KU JOSEPH WEIYEH 发明人 KU JOSEPH WEIYEH
分类号 H04L12/26;(IPC1-7):G06F11/00 主分类号 H04L12/26
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