发明名称 |
Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration |
摘要 |
Circuit configurations for testing transistors are arranged in the scribe line between integrated circuits on a semiconductor wafer. In order to increase the number of testable transistors while consuming little surface area, the transistors are arranged in a matrix in at least two rows. The drain-source paths of the transistors in the first row are connected between pads, and their gate connections are connected to a common pad. The drain-source paths of the transistors in the second row are connected firstly to one of the pads, and are secondly jointly connected to a further pad. Their gate connections are likewise connected to a further pad. The matrix-like arrangement of the transistors can be extended by using additional rows.
|
申请公布号 |
US6529031(B2) |
申请公布日期 |
2003.03.04 |
申请号 |
US20010876706 |
申请日期 |
2001.06.07 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
GERSTMEIER GUENTER;ROSSKOPF VALENTIN |
分类号 |
G11C29/00;H01L23/544;(IPC1-7):G01R31/26 |
主分类号 |
G11C29/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|