| 摘要 |
A self-timing memory circuit with supply degradation compensation comprising a first self-timing circuit and a second self-timing circuit. The first self-timing circuit may be configured to generate a first signal that may be minimally affected by power supply degradation and/or variation. The second self-timing circuit may be configured to generate a second signal, where an effect of the power supply degradation and/or variation on the second signal is maximized.
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