| 摘要 |
PURPOSE: To suppress the occurrence of a vertical streak caused by overlap sampling. CONSTITUTION: A horizontal drive circuit 17 has a shift resistor which shifts in synchronous with a first clock signal HCK to sequentially output shift pulses from each shift stage, first switches which take out a second clock signal DCK in response to the shift pulses outputted sequentially from the shift resistor, and second switches which sequentially sample an inputted video signal in response to the second clock signal DCK taken out by each of the first switches and then supply it to each signal line 12. Further, an external clock generating circuit 18 which, provided outside a panel 33, externally supplies the first clock signal HCK to a horizontal drive circuit 17, and an internal clock generating circuit 19 which, formed inside the panel 33, internally supplies the second clock signal DCK to the horizontal drive circuit 17, are arranged.
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