发明名称 |
METHOD FOR ADJUSTING DELAY IN SEMICONDUCTOR DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To quickly perform such delay adjustment in which a delay value does not shift even though fluctuations of temperature and voltage at operation and process dispersion at manufacturing occur concerning a path provided with the complete delay values when designed on a circuit of a semiconductor device. SOLUTION: A delay adjusting method is provided separately with a gate delay adjustment process S2 and a wiring delay adjustment process S3, individually adjusts gate delay and wiring delay, is provided with a gate delay shift allowable quantity calculation process S5 and a wiring delay shift allowable quantity calculation process S7, calculates delay shift allowable quantity in each path to perform necessary minimum delay adjustment and thereby, quickly adjusts path delay including balance between gate delay and wiring delay.
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申请公布号 |
JP2003058589(A) |
申请公布日期 |
2003.02.28 |
申请号 |
JP20010247504 |
申请日期 |
2001.08.17 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
SHIROGAICHI TAKESHI;HINATSU YUJI |
分类号 |
G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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主权项 |
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地址 |
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