| 摘要 |
<p>PROBLEM TO BE SOLVED: To realize a semiconductor memory in which input/output of data can be performed in a DDR mode using a low speed tester. SOLUTION: An internal clock generating circuit (3) generates internal clock signals (CLKP, CLKN, CLK) at double the speed of an external clock signal in a test mode. An input/output circuit (6) performs input/output of data in a DDR mode conforming to an internal clock signal of this double speed. Especially, an output drive signal CLKO having double the frequency of the internal clock signal, also, input/output of data is performed in a DDR mode and at double the speed of an external clock signal by generating a data strobe signal DQS being double the speed of an external data strobe signal.</p> |
