发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with an embedded impurity layer for an α ray soft error measure and provided with an SRAM capable of reducing taps for grounding for each cell. SOLUTION: An embedded n-type layer B-N is disposed as an intermediate layer on a p-type semiconductor substrate P-sub. On the n-type layer B-N, a p-type well region PWEL is uniformly provided. On the n-type layer B-N, the p-type substrate P-sub is present for prescribed thickness, and the p-type well region PWEL and an n-type well region NWEL are provided in equal depth. A CMOS circuit is constituted of respective wells. A power supply voltage VDD is supplied to the source of a P channel MOS transistor Qp and the well region NWEL. Also, since the well region PWEL is connected to the p-type substrate P-sub, it does not float. Thus, for supply of a ground potential VSS to the well region PWEL, the number of the taps is reduced.
申请公布号 JP2003060071(A) 申请公布日期 2003.02.28
申请号 JP20010241287 申请日期 2001.08.08
申请人 SEIKO EPSON CORP 发明人 KUWAZAWA KAZUNOBU
分类号 H01L27/08;H01L21/8238;H01L21/8244;H01L27/092;H01L27/11 主分类号 H01L27/08
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