发明名称 DIGITAL BROADCASTING RECEIVER
摘要 <p>PROBLEM TO BE SOLVED: To provide a digital broadcasting receiver where memory capacity is reduced. SOLUTION: In a guard interval correlation circuit 206, a signal switching section 312 for changing an I/O signal to a delay memory 302 is provided. Immediately after power on, immediately after channel change, or the like, a region corresponding to the effective symbol period of the delay memory 302 is used for detecting a guard interval period. Then, although a region that is slightly larger than a guard period is used for detecting the guard interval period after the guard interval period is detected, other regions can be used for other circuits connected to a terminal 321. Other circuits carry out the processing of a stage after the guard interval correlation circuit 206 like an AFT circuit or the like, thus processing a memory that was connected to other circuits conventionally by the delay memory 302, and hence reducing the memory.</p>
申请公布号 JP2003060612(A) 申请公布日期 2003.02.28
申请号 JP20010246577 申请日期 2001.08.15
申请人 SANYO ELECTRIC CO LTD 发明人 YOSHINAGA MASAYUKI;IWASAKI TOSHIYA;TANAKA GOJI
分类号 H04H20/00;H04H40/18;H04J11/00;H04L7/00;H04N5/44;H04N5/455;(IPC1-7):H04J11/00;H04H1/00 主分类号 H04H20/00
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