发明名称 MEMORY SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress the endurance deterioration of a ferroelectric memory provided in a memory system and to improve data holding characteristic. SOLUTION: In the ferroelectric memory 10, a set data on the write time of data into a memory cell is stored in advance. This set data is two kind of data different in the case of being instructed when power is on and when power off. When power is supplied, the set data stored in the ferroelectric memory 10 is stored and held in a latch circuit 11 by a control circuit 9. Based on the set data held in this latch circuit 11, data writing of the ferroelectric memory 10 is performed separately in the case of being instructed when power is on and when power off. Consequently, the operation of the ferroelectric memory 10 can be controlled with the operation timing corresponding to the operation situation. Further, unnecessary stress application to the ferroelectric memory cell 10 when the power is on is prevented and the data holding characteristic after power off is improved.
申请公布号 JP2003059261(A) 申请公布日期 2003.02.28
申请号 JP20010252523 申请日期 2001.08.23
申请人 发明人
分类号 G06F12/00;G11C11/22;(IPC1-7):G11C11/22 主分类号 G06F12/00
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