| 摘要 |
Disclosed is a timing circuit for generating a clock signal which indicates a timing for discriminating a data signal. The timing circuit includes a branching circuit for branching a data signal in two directions, a duty monitoring circuit for monitoring the duty of a first data signal output from the branching circuit, a duty varying circuit for varying the duty of a second data signal output from the branching circuit, a control circuit for controlling the duty varying circuit on the basis of the duty information output from the duty monitoring circuit so that the duty of the data signal to be output has a predetermined value and a clock signal generator for generating the clock signal for discriminating a data signal which is synchronous with the data signal output from the duty varying circuit.
|
