| 摘要 |
<p>An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Zn) into a first part (msb(Zn)) that is the power of 2 immediately lower than or equal to the input signal and a second part (Zn - msb(Zn)) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.</p> |
