发明名称 Memory device and memory system
摘要 In a memory device which is used with the memory device connected to a data bus, the memory device includes an active termination circuit for terminating the memory device when the active termination circuit is electrically put into an active state and for unterminating the memory device when the active termination circuit is electrically put into an inactive state. The memory device further includes a control circuit for controlling the active termination circuit to electrically put the active termination circuit into the active state or the inactive state.
申请公布号 US2003039151(A1) 申请公布日期 2003.02.27
申请号 US20020227647 申请日期 2002.08.23
申请人 MATSUI YOSHINORI 发明人 MATSUI YOSHINORI
分类号 G11C11/409;G06F3/00;G06F12/00;G06F13/16;G11C7/10;G11C11/401;G11C11/4063;G11C11/407;H03K19/0175;(IPC1-7):G11C7/00 主分类号 G11C11/409
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