发明名称 |
POWER RAISING CIRCUIT |
摘要 |
An iterative power raising circuit, such as a squarer (10) comprises a modul e (13, 14) able to subdivide the respective input signal (Zn) into a first par t (msb(Zn)) that is the power of 2 immediately lower than or equal to the inpu t signal and a second part (Zn - msb(Zn)) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme i s selectively controllable in order selectively to vary the precision with whi ch the output value (Y) is calculated.
|
申请公布号 |
CA2457201(A1) |
申请公布日期 |
2003.02.27 |
申请号 |
CA20022457201 |
申请日期 |
2002.08.14 |
申请人 |
TELECOM ITALIA S.P.A. |
发明人 |
ETTORRE, DONATO;MELIS, BRUNO;RUSCITTO, ALFREDO |
分类号 |
G06F7/552;H03K19/173;(IPC1-7):G06F7/552 |
主分类号 |
G06F7/552 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|