Scan flip-flop with bypass of the memory cell of the flipflop

摘要

The invention proposes to provide core scan chain functionality of an integrated circuit by providing at least one scan flip-flop (10), each having a functional layer between an input port (PI) and at least one output port (Q,QN) and a storage layer between a scan input port (SI) and one of at least one output port (Q,QN) constructed to be used within a scan chain, modifying said scan flip-flop (10) by adding a bypass to a non-inverted and separate scan output port (SO) and implementing each of such modified scan flip-flops in the integrated circuit by creating a scan chain using the scan input port (SI) and the scan output port (SO). Additionally, delay measurement and characterization can be performed. Also improved resetting is possible to avoid power-peaks by a delayed distribution of the reset pulses.