| 摘要 |
PROBLEM TO BE SOLVED: To reduce a circuit scale and shorten a time required for a burn-in test, in a semiconductor device mounted mixedly with a logic circuit and a memory on the same chip. SOLUTION: A control circuit 4 for controlling an operation mode in the test for the logic circuit 2 and the DRAM 3 is provided on the same chip mounted with the logic circuit 2 and the DRAM 3, a scanning test mode is set in the burn-in test in the logic circuit 2, a burn-in test mode is set therein in the DRAM 3. A circuit for generating an input signal exclusive to the burn-in test is not provided in the logic circuit 2, and the burn-in test is carried out using an input signal for the scanning test. The circuit scale of the logic circuit 2 is reduced thereby, and the number of input signals to a semiconductor device 1 is thereby reduced in the burn-in test, to allow the burn-in tests for both the logic circuit 2 and the DRAM 3 to be carried out concurrently.
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