| 摘要 |
A high-voltage differential input receiver interfaces with an external channel. The differential input receiver includes a first stage, a second stage, and a third stage, which incrementally reduce in stages the common mode of a differential signal received from the external channel. During a power-down mode, clamping circuits in the differential input receiver clamp the voltage at nodes in the differential input receiver, and clamp the differential output from the first stage, to a predetermined voltage to prevent electrical overstress of oxide layers of n-channel and p-channel devices in the differential input receiver. Consequently, electrical overstress of oxide layers is prevented, and the voltage swing level of inputs from the external channel is reduced in stages from a higher voltage level to a lower voltage level.
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