Multiport FIFO with programmable width and depth

摘要

A circuit comprising a memory array and a control circuit. The memory array generally comprises a plurality of storage queues. Each of the storage queues may be configured to (i) receive and store an input data stream and (ii) present an output data stream. The storage queues may be configured to operate either (i) independently or (ii) in combination to store the input data streams, in response to one or more control signals. The control circuit may be configured to present the one or more control signals to control an operation of the plurality of storage queues. The control signals may be configured to control the configuration of the plurality of storage queues.