Phase-lock loop with independent phase and frequency adjustments

摘要

A PLL is provided with separate phase and frequency adjustment circuits to adjust the frequency of a produced internal clock independently from adjusting its phase. The phase adjustment circuit determines a phase error between the internal clock and an external clock, and averages the phase error over a predetermined time period to produce the corresponding control current. The frequency adjustment circuit detects the difference between the frequency of the internal clock and the frequency of the external clock to determine a frequency error. An accumulator accumulates the frequency error during the predetermined time period to produce the corresponding control current. Based on values of the control currents produced by the phase and frequency adjustment circuits, a current calculator calculates a resulting value of the control current to be applied to a CCO to modify its frequency so as reduce the frequency and phase differences.