| 摘要 |
A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about -9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.
|
