发明名称 |
High withstand voltage insulated gate N-channel field effect transistor |
摘要 |
A high withstand voltage insulated gate N-channel field effect transistor has a P-type semiconductor substrate and an N-type epitaxial layer formed on the semiconductor substrate. An N-type source region having a high concentration is formed on the epitaxial layer. An N-type drain region having a high concentration is formed on the epitaxial layer and is spaced-apart from the source region. A channel forming region is disposed between the source region and the drain region. A gate insulating film is disposed over the source and drain regions and the channel forming region. A gate electrode is formed through the channel forming region and the gate insulating film. An N-type low concentration region is formed between the drain region and the channel forming region. A second insulating film is formed on the low concentration region and has a thickness greater than that of the gate insulating film. A P-type buried layer is formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source region, the drain region, the channel forming region, and the second insulating film. A P-type well layer is formed in a region under the source region and the channel forming region and is formed in a part of a region under the second insulating film so as to surround the drain region.
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申请公布号 |
US6525376(B1) |
申请公布日期 |
2003.02.25 |
申请号 |
US19990235670 |
申请日期 |
1999.01.22 |
申请人 |
SEIKO INSTRUMENTS INC. |
发明人 |
HARADA HIROFUMI;OSANAI JUN |
分类号 |
H01L21/336;H01L21/8222;H01L21/8248;H01L21/8249;H01L27/06;H01L29/08;H01L29/10;H01L29/423;H01L29/78;(IPC1-7):H01L29/76;H01L29/94;H01L23/58 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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