Semiconductor integrated circuit device including a clock synchronous type logical processing circuit

摘要

A first circuit group for generating a dock signal, and a second circuit group for carrying out a transferring operation and a logical processing operation on a signal in accordance with this clock signal are arranged, and operation voltage sources of these circuit groups are made individually settable. Thus, the operation speeds of the first circuit group and the second circuit group are individually adjusted so as to eliminate a problem of an erroneous operation due to a racing through an operation. An erroneous operation due to a racing caused by dock skew can be reliably prevented through an external operation.