| 摘要 |
Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.
|
