| 发明名称 |
Method of reducing electrical shorts from the bit line to the cell plate |
| 摘要 |
A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.
|
| 申请公布号 |
US6524907(B2) |
申请公布日期 |
2003.02.25 |
| 申请号 |
US20020171369 |
申请日期 |
2002.06.13 |
| 申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
PAREKH KUNAL R.;DENNISON CHARLES H.;HONEYCUTT JEFFREY W. |
| 分类号 |
H01L21/02;H01L21/768;H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
