发明名称 |
Decoder and decoding method |
摘要 |
A decoder has a reduced circuit dimension that does not adversely affect the decoding performance of the circuit. The decoder includes an addition/comparison/selection circuit added to give the log likelihood and adapted to compute a correction item expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood.
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申请公布号 |
US6525680(B2) |
申请公布日期 |
2003.02.25 |
申请号 |
US20010876701 |
申请日期 |
2001.06.07 |
申请人 |
SONY CORPORATION |
发明人 |
YAMAMOTO KOUHEI;MIYAUCHI TOSHIYUKI |
分类号 |
G06F11/10;H03M13/45;(IPC1-7):H03M7/00;H03M13/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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