发明名称 |
DATA REPRODUCING DEVICE, AND PROGRAM |
摘要 |
PROBLEM TO BE SOLVED: To provide a data reproducing device of lower electric power by using a refresh-control circuit in which a DRAM can perform a required hold operation with low electric power. SOLUTION: In a DRAM refresh-control circuit, a write address and a read- out address outputted from a DRAM address generating section are inputted to constitute FIFO for data. When it is determined that the value of a refresh- counter is of a higher order than a write address and is of a lower order than a read-out address, a stop signal is issued to a refresh-executing section to stop needless refresh-operation.
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申请公布号 |
JP2003051185(A) |
申请公布日期 |
2003.02.21 |
申请号 |
JP20010236831 |
申请日期 |
2001.08.03 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
KATOU NOBUYOSHI |
分类号 |
G06F12/16;G06F12/00;G11B20/10;G11C11/406;(IPC1-7):G11C11/406 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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