发明名称 CIRCUIT INTEGRE, NOTAMMENT CELLULE MEMOIRE DRAM AVEC CONTACT A FAIBLE FACTEUR DE FORME ET PROCEDE DE FABRICATION
摘要 The invention concerns an integrated circuit comprising a substrate (1), at least a capacitor (9) arranged above the substrate (1) and provided with a first electrode (5), a second electrode (8), and a dielectric (7) arranged between the two electrodes, at least a connecting feedthrough between the substrate (1) and a conductive level located above the capacitor (9), and a dielectric material covering the substrate (1) and enclosing the capacitor (9) and the feedthrough. The feedthrough comprises a first portion (18) arranged between the substrate and the lower level of the first electrode, a second portion (6) arranged between the lower level of the first electrode and the upper level of the first electrode, and a third portion (12) in contact with the first electrode and flush with said conductive level, the second portion being made of the same material as the first electrode of the capacitor.
申请公布号 FR2828763(A1) 申请公布日期 2003.02.21
申请号 FR20010010867 申请日期 2001.08.16
申请人 STMICROELECTRONICS SA 发明人 MAZOYER PASCALE;CAILLAT CHRISTIAN
分类号 H01L21/28;H01L21/768;H01L21/8242;H01L27/108 主分类号 H01L21/28
代理机构 代理人
主权项
地址