| 摘要 |
PROBLEM TO BE SOLVED: To provide a data recovery circuit and a method thereof which are capable of reducing locking time and jitter. SOLUTION: The data recovery circuit includes a frequency-locked loop, a locking detector, a delay-locked loop and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal with the frequency of the input signal and generates a frequency locking signal representing that the input signal is frequency-locked with the internal clock signal. The lock detector determines whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal, locks the phase of the internal clock signal with the phase of the input signal, and generates a recovery locking signal. The data determination circuit receives the recovery locking signal as a clock signal, receives the input signal in response to the clock signal and outputs the input signal as the output data. |
