| 摘要 |
PROBLEM TO BE SOLVED: To generate a program to perform register allocation to instruction word strings arranged by instruction scheduling, so that bit transition of bit expression of register specification is reduced, and to especially reduce power consumption in the case of erroneous caching, etc., in a cluster configuration VLIW(very long instruction word) processor. SOLUTION: In a register allocation processing after the instruction scheduling by an instruction scheduling processing function 13 by providing a register allocation processing function 15, the register allocation which takes into consideration the bit transition of the bit expression of the register specification is performed. In the cluster configuration VLIW, an object program capable of reducing the bit transition in a cache line, for example, in the case of the erroneous instruction caching is generated by recognizing relation between operands of instructions to be executed in parallel, through clustering and allocating clusters by referring to the register number of a cluster other than the allocated one and selecting the register number with reduced bit transition.
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