发明名称 BUFFER MEMORY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To obtain a buffer memory circuit, capable of minimizing malfunction time due to temporary noise, etc., and being automatically restored so as not to exert adverse effects on communications afterwards. SOLUTION: Data quantity in a dual port memory 1 is detected with an address difference detecting part 60 and a buffer capacity monitoring part 61, and the malfunctions of a write address and a read address are detected by comparing the pieces of data quantity with an address control operation comparing part 7. In addition, the malfunctions of the write address and the read address which cannot be detected with an address control part 6 are detected using a parity generating part 3, by adding a parity shifted by one address from write data.</p>
申请公布号 JP2003050748(A) 申请公布日期 2003.02.21
申请号 JP20010236524 申请日期 2001.08.03
申请人 NEC CORP 发明人 KUBOTA TATSUYA
分类号 G06F12/16;H04L12/70;(IPC1-7):G06F12/16;H04L12/56 主分类号 G06F12/16
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