摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor memory device of memory cell structure in which cell area is reduced. SOLUTION: A gate of a NMOS transistor N1 is connected to a storage terminal Na, and a gate of a NMOS transistor N2 is connected to a storage terminal Nb. Sources of the NMOS transistors N1 and N2 are connected commonly to an internal terminal Nc and GND. Potentials of back gate terminals BN1 and BN2 of the NMOS transistors N1 and N2 are set to a ground potential GND. When PMOS transistors P1, P2 are in ON, OFF states, the storage terminal Na can be kept at a 'H' state by the PMOS P1, and the storage terminal Nb can be kept logically at a 'L' state by a gate leak current flowing from a gate of the NMOS transistor N2 to a semiconductor substrate.
|