High speed, low latency bus modulation method and apparatus including a semiconductor structure for implementing same

摘要

A method and apparatus for bus compression in an array processing system, involving providing a data bus making multiple data bus connections between two separate processing modules; compressing bus signals outputted by at least one of the processing modules with an associated bus modulator effective to permit concurrent transfer of a plurality of bits of information per connection; transferring the compressed signals via the data bus to a bus demodulator associated with the other processing module, wherein the demodulator reconstructs the bus signals before inputting the signals to the other processing module; wherein at least one of the processing modules is formed at least in part in CMOS in a unique semiconductor structure.