| 摘要 |
<p>Method of manufacturing a semiconductor device comprising a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory comprising a memory cell with a gate structure (4) with an access gate (21) and a gate structure (3) with a control gate (5) and a charge storage region, such as a floating gate (6) situated between the control gate (5) and the semiconductor body (1). In this method on the surface (2) of the semiconductor body (1) a first one of said gate structures is formed with side walls (10,11) extending substantially perpendicular to the surface. Then a conductive layer (14) is deposited on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer (15) is patterned so as to form at least a part of the other gate structure adjoining only a first one (10) of the side walls of the first gate structure. The patterning of the planarized conductive layer is performed in that, an etch mask (16) is formed on the first gate structure and the planarized conductive layer which etch mask leaves the planarized conductive layer next to said first side wall (10) uncovered and covers the planarized conductive layer next to the side wall (11) opposite to the first side wall. Then the planarized conductive layer is etched back so as to expose an upper portion (17) of said first side wall, the etch mask is removed, a spacer (20) is formed on the exposed upper portion (17) of said first side wall and the conductive layer (18) is etched anisotropically using the spacer as a mask, whereby the conductive layer next to the spacer and next to the side wall of the first gate structure opposite to said first side wall is removed. Thus very small memory cells can be realized.</p> |
