发明名称 |
METHOD FOR FABRICATING FERROELECTRIC MEMORY TRANSISTOR |
摘要 |
PURPOSE: A method for fabricating a ferroelectric memory transistor is provided to form a source/drain junction properly connected to a conductive channel of a transistor by etching a bottom electrode without damaging an underlying substrate. CONSTITUTION: A silicon substrate(20) on which a plurality of active areas are formed is prepared. A gate insulation layer(22) is deposited on the substrate. A polysilicon layer(24) is deposited over the gate insulation layer. A source region, a drain region and a gate electrode are formed. A bottom electrode material layer is deposited and the bottom electrode is finished without damaging the underlying gate insulation layer and the silicon substrate. A ferroelectric material layer is deposited on the bottom electrode. A top electrode material layer is deposited on the ferroelectric material. The transistor is finished after passivation oxide deposition, contact hole etching and metallization.
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申请公布号 |
KR20030015143(A) |
申请公布日期 |
2003.02.20 |
申请号 |
KR20020047604 |
申请日期 |
2002.08.12 |
申请人 |
SHARP CORPORATION |
发明人 |
HSU SHENGTENG;LI TINGKAI;ULRICH BRUCEDALE |
分类号 |
H01L27/105;H01L21/00;H01L21/28;H01L21/302;H01L21/336;H01L21/461;H01L21/822;H01L21/8239;H01L21/8242;H01L21/8246;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L27/105 |
主分类号 |
H01L27/105 |
代理机构 |
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代理人 |
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地址 |
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