FLASH MEMORY DEVICE WITH INCREASE OF EFFICIENCY DURING AN APDE (AUTOMATIC PROGRAM DISTURB AFTER ERASE) PROCESS

摘要

A source resistor or a positive voltage is couples to the source and a negative bias voltage is applied at the substance or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. In a system and method for performing an APDE (Automatic Program Disturb after Erase) process, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A bit line APDE (Automatic program Disturb after Erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A control gate APDE (Automatic Program Disturb after Erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. Alternatively, the source is coupled to the control gate for each flash memory cell in a self-biasing configuration such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.