发明名称 |
Bump layout on silicon chip |
摘要 |
A bump layout on the active region of a driver IC for increasing overall bump count. The layout fits IC packages that have a narrow and long body profile. Bumps are positioned close to the long side and central regions of the active region so that low marking pressure on the shorter sides of the package during chip-glass bondage is avoided. Dummy bumps may also be positioned close to the shorter sides of the package so that pressure distribution is optimized during chip-glass bondage. |
申请公布号 |
US2003034168(A1) |
申请公布日期 |
2003.02.20 |
申请号 |
US20020064575 |
申请日期 |
2002.07.29 |
申请人 |
YANG WEN-CHIH;SU FENG-CHENG;YANG CHIN-CHEN |
发明人 |
YANG WEN-CHIH;SU FENG-CHENG;YANG CHIN-CHEN |
分类号 |
H01L23/50;(IPC1-7):H01L23/02 |
主分类号 |
H01L23/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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