发明名称 |
STACKED THIN SMALL OUTLINE PACKAGE |
摘要 |
PURPOSE: A stacked thin small outline package is provided to simplify a fabrication process of a connection pin by stacking a plurality of thin small outline packages having compatible chip selection pins and compatible dummy pins. CONSTITUTION: A stacked thin small outline package(300) is formed by stacking vertically a plurality of thin small outline packages. The thin small outline package has a couple of package bodies(315,325) including a couple of semiconductor chips(311,321) and a plurality of connection pins projected from the package bodies(315,325). The connection pins are electrically connected with bonding pads(314,324) of the semiconductor chips(311,321) through wires(313,323). A chip selection pin(319) corresponds to a dummy pin(328). The stacked thin small outline package(300) is formed with a thin small outline package(310) and one ore more stacked thin small outline packages(320). |
申请公布号 |
KR20030014863(A) |
申请公布日期 |
2003.02.20 |
申请号 |
KR20010048747 |
申请日期 |
2001.08.13 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
BAE, GYU HAN;JANG, OK HYEONG;KIM, SEONG HWAN;KO, JUN YEONG |
分类号 |
H01L23/12;(IPC1-7):H01L23/12 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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