发明名称 MOS-gesteuerte Leistungsanordnung mit versenktem Gate und Verfahren zur Herstellung
摘要 A semiconductor device having a concavity formed by LOCOS technique, in which defects induced due to the LOCOS oxidation step or a following heat-treatment step are suppressed, is disclosed. An n<+> type region (31), the impurity concentration of which is caused to be 1 x 10<19> cm<-3> or more, is formed in an n<-> type semiconductor layer (2). By means of this, defects (61, 62) occur within the n<+> type region (31) or in a proximity of the boundary of the n<+> type region (31) and the n<-> type semiconductor layer (2). The defects (61) and (62) trap contaminant impurities taken into the wafer during the manufacturing steps, and cause contaminant impurities existing in the proximity of a concavity of the semiconductor layer (2) surface to be reduced. As a result thereof, defect occurrence in the proximity of the concavity can be suppressed, and occurrence of leakage and degradation in breakdown voltage between drain and source accompanying defect occurrence in a channel region can be suppressed. <IMAGE>
申请公布号 DE69625740(D1) 申请公布日期 2003.02.20
申请号 DE1996625740 申请日期 1996.04.25
申请人 DENSO CORP., KARIYA 发明人 OKABE, NAOTO;YAMAMOTO, TSUYASHI;KATAOKA, MITSUHIRO
分类号 H01L21/322;H01L21/336;H01L29/739;H01L29/78 主分类号 H01L21/322
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