发明名称 |
Data separation and decoding device |
摘要 |
A clock recovery circuit (4) is provided with an STC counter, an adder for setting the initial value of the STC counter by adding the value of a PCR and the multiplexing delay time; a subtracter for subtracting the multiplexing delay time from the output of the STC counter; a latched STC register for latching the subtraction result of the subtracter; a PCR register for latching the value of the PCR; and a PWM for controlling the frequency of an external clock oscillation source that supplies a clock signal to the STC counter. The clock oscillation source (10) is provided with an LPF (11) and a VCO (12), wherein a clock signal outputted from the VCO is supplied to the STC counter and a timer within a stream multiplexing circuit. The clock signal outputted from the clock oscillation source is a reference clock signal of an MPEG system. Thereby, the scale of the entire device can be reduced by reducing the number of separation and decoding circuits. <IMAGE> |
申请公布号 |
EP1284578(A1) |
申请公布日期 |
2003.02.19 |
申请号 |
EP20020017480 |
申请日期 |
2002.08.05 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
HONMURA, HIROSHI;MIYAMOTO, ATSUSHI |
分类号 |
H04J3/00;H04N5/44;H04N7/08;H04N7/081;H04N7/173;H04N19/00;H04N19/42;H04N19/423;H04N19/44;H04N19/46;H04N19/48;H04N19/70;H04N19/85 |
主分类号 |
H04J3/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|