| 摘要 |
A bi-directional full duplex clocked bus including eight data lines, a clock line and a control line. The bus signals are low level differential with suitable drivers and receivers. The bus operation includes a protocol of sending groupings of eight bytes transmissions where a byte is sent on the rising and the falling edges of the clock signal. When reading the received data, delayed clocks are used that are formed at the center of both of the received clock signal phases. The delayed clocks may be used to output data on the outputs lines. The delayed clocks are arranged to be symmetrical with substantially no skew and centered to the phases of the received clock signal.
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