发明名称 |
Method for manufacturing wafer level chip size package |
摘要 |
A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging. |
申请公布号 |
US6521485(B2) |
申请公布日期 |
2003.02.18 |
申请号 |
US20010760763 |
申请日期 |
2001.01.17 |
申请人 |
WALSIN ADVANCED ELECTRONICS LTD |
发明人 |
SU SPENCER;LAI JAMES;CHIEN-TSUN LIN;CHEN CAPTAIN;CHEN ALLEN;YANG C.S.;CHAO-CHIA CHANG;HSIA KEVIN |
分类号 |
H01L23/31;(IPC1-7):H01L21/44;H01L21/48;H01L21/50 |
主分类号 |
H01L23/31 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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