发明名称 |
High-speed digital accumulator with wide dynamic range |
摘要 |
A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a preceding clock period. The accumulator also includes at least one second stage having incrementer/decrementer means for performing an increment, decrement or identity operation on a most significant part of the output of the accumulator. The incrementer/decrementer means includes logic means for triggering the increment, a decrement or identity operation on the most significant part of the accumulator output based on a decision made on results obtained at the previous clock period.
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申请公布号 |
US6523057(B1) |
申请公布日期 |
2003.02.18 |
申请号 |
US19990307083 |
申请日期 |
1999.05.07 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
SAVO PIERANDREA;ZANGRANDI LUIGI;MARCHESE STEFANO |
分类号 |
G06F7/505;G06F7/00;G06F7/50;G06F7/509;(IPC1-7):G06F7/50 |
主分类号 |
G06F7/505 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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