发明名称 |
High performance integrated varactor on silicon |
摘要 |
A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.
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申请公布号 |
US6521939(B1) |
申请公布日期 |
2003.02.18 |
申请号 |
US20000672764 |
申请日期 |
2000.09.29 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
YEO KIAT-SENG;GENG CHUN QI;CHEW KOK-WAI;DO MANH-ANH;MA JIAN GUO |
分类号 |
H01L21/334;H01L27/08;H01L29/94;(IPC1-7):H01L27/108;H01L29/76 |
主分类号 |
H01L21/334 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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