| 摘要 |
In a wiring designing method for a semiconductor integrated circuit, a signal line (201) is wired. Adjacent signal lines (204, 205), in which output ends (204o, 205o) are opened, are mounted adjacently to the signal line (201). A capacitance is calculated which are formed by the signal line (201) and the adjacent lines (204, 205). Line lengths (L2, L3) of the adjacent lines (204, 205) are adjusted in accordance with the capacitance. The capacitance is changed by the adjustment of the line lengths (L2, L3). Accordingly, it is possible to adjust the capacitance formed by the two signal lines adjacent to each other and a delay amount of the signal flowing through the signal line.
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