| 摘要 |
A dual-loop PLL circuit is provided with a clamping circuit 12, an A/D conversion circuit 14, a reference color burst outputting circuit 18, a PLL circuit 24, and phase detecting circuit 34. The phase of a reference color burst KK outputted from the circuit 18 is changed at a slice level SL, and the level SL is changed by a reference phase value in the phase detecting circuit 34. The sampling clocks outputted from the PLL circuit 24 to the A/D conversion circuit 14 are converted to a signal of a frequency of 4 Fsc, and the phase of the signal can be changed continuously by using the reference phase value. In addition, since the phase of the sampling clocks can be adjusted to a desired value and the output signal of the A/D conversion circuit 14 can be converted onto a prescribed color difference signal by a signal conversion circuit and outputted, the color difference signals can be demodulated easily with high accuracy.
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