发明名称 |
Mos transistor and dram cell configuration |
摘要 |
A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.
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申请公布号 |
US6521935(B2) |
申请公布日期 |
2003.02.18 |
申请号 |
US20010027524 |
申请日期 |
2001.12.26 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
KRAUTSCHNEIDER WOLFGANG;SCHLOESSER TILL;WILLER JOSEF |
分类号 |
H01L21/336;H01L21/8242;H01L27/108;H01L29/78;H01L29/786;(IPC1-7):H01L27/108;H01L29/76;H01L29/94;H01L31/119 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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